1. Field of the Invention
The present invention relates to a solid-state image pickup device, such as a CMOS-type solid-state image pickup device, a CCD-type solid-state image pickup device, and the like, for use in various cameras, such as, for example, video cameras, surveillance cameras, front-door intercom cameras, in-vehicle cameras, cameras for videophones, cameras for mobile telephones, and the like, camera systems using these cameras, or the like. The present invention also relates to an electronic information apparatus comprising the solid-state image pickup device.
2. Description of the Related Art
At present, CMOS-type solid-state image pickup devices generally used are provided with a diffusion layer having a floating potential, which is called a floating diode, on a semiconductor substrate. The diffusion layer converts incident light to electricity. Electric charges generated by this photoelectric conversion are converted to a voltage by the capacitance component of the PN junction of the diffusion layer. A signal component is then output depending on the voltage of the electric charge. Thereafter, by applying a reset pulse (reset control signal) to the gate of a reset transistor, unnecessary electric charges accumulated in the floating diode portion is discharged through the reset drain portion so as to reset the potential of electric charges accumulated in the floating diode portion to a predetermined reset voltage.
CCD-type solid-state image pickup devices comprise CCD pixels arranged one-or two-dimensionally on a semiconductor substrate. Electric charges generated by photoelectric conversion by each CCD pixel are transferred through an electric charge transfer section to an electric charge accumulation region having a floating potential. A signal component corresponding to the voltage of the electric charges accumulated in the electric charge accumulation region is output to an output circuit. Thereafter, by applying a reset pulse (reset control signal) to the gate of a reset transistor, unnecessary electric charges accumulated in the floating diode portion is discharged through the reset drain portion so as to reset the potential of electric charges accumulated in the floating diode portion to a predetermined reset voltage.
FIG. 3 is a circuit diagram showing a configuration of a unit pixel in a conventional CMOS-type solid-state image pickup device.
Each unit pixel comprises a select switch transistor 1, a reset transistor 2, a floating diode 3, and an amplification transistor 4. The CMOS-type solid-state image pickup device is provided with a plurality of unit pixels arranged in a matrix having rows and columns on a semiconductor substrate.
The select switch transistor 1 has a source connected to a column signal line 5, a drain connected to the source of the amplification transistor 4, and a gate connected to a row signal line 6. A select pulse is used to select the row signal line 6. The select switch transistor 1 connected to the selected row signal line 6 is then driven.
The reset transistor 2 has a source connected to an electric charge accumulation region N1, a drain connected to the application portion of a voltage reset drain (reset voltage), and a gate connected to a reset pulse signal line 7. A reset pulse is used to reset the electric charge accumulation voltage of the electric charge accumulation region N1 through the reset transistor 2.
The floating diode 3 comprises a PN junction portion, in which electric charges generated by photoelectric conversion are accumulated in the electric charge accumulation region N1 having a floating potential.
The amplification transistor 4 has a source connected to the drain of the select switch transistor 1, a drain connected to a power source voltage, and a gate (the control terminal) connected to the electric charge accumulation region N1. The amplification transistor 4 outputs a signal voltage amplified depending on an electric charge accumulation voltage corresponding to the amount of incident light which has been photoelectrically converted by the floating diode 3.
The image pickup device is provided with a plurality of column signal lines 5 (vertical signal lines) arranged in parallel to each other. A vertical select transistor (not shown) is used to select each column signal line 5 so that unit pixels on a corresponding column of the two-dimensional matrix are selected. The select pulse row signal line 6 and the reset pulse signal line 7 are provided for each row of the two-dimensional matrix of unit pixels.
FIG. 4 is a timing chart for explaining an operation of the CMOS-type solid-state image pickup device of FIG. 3.
When a reset pulse goes to a high level so that a positive voltage is applied to the gate of the reset transistor 2, a short circuit electrically occurs between the reset drain and the floating diode 3, and as a result, the potential of the electric charge accumulation region N1 of the floating diode 3 is fixed (reset) to the potential of the voltage reset drain.
Next, when the reset pulse goes to a low level, the electric charge accumulation region N1 of the floating diode 3 is potentially shut off from the voltage reset drain. In this case, when light enters the floating diode 3, electric charges are generated in proportion to the amount of the incident light and the electric charges are converted to a negative voltage. As a result, the potential of the electric charge accumulation region N1 of the floating diode 3 which has been reset to the voltage reset drain is gradually lowered.
After a predetermined exposure time, when a select pulse goes to a high level, the select switch transistor 1 of each unit pixel on a row is selected through the corresponding row signal line 6. A signal voltage corresponding to the difference in potential between the voltage reset drain and the floating diode 3 is output as a signal component through a selected column signal line 5. Thereafter, when a reset pulse goes to the high level again, the electric charge accumulation region N1 of the floating diode 3 is reset to the potential of the voltage reset drain. The above-described operation is carried out for each frame period (e.g., 30 ms).
In general, the high level of the above-described reset pulse and select pulse is the power source voltage, and the low level thereof is 0 V, where the power source voltage is assumed to be 3 V. The voltage of the reset drain is often the same as the power source voltage.
As the reset transistor 2, a depletion-type transistor is generally used, in which when the high level of a reset pulse applied to the gate is the power source voltage, conduction can be obtained between the drain (reset drain) having the power source voltage and the source (floating diode).
FIG. 5 is a graph showing a relationship between the gate voltage and the potential under the gate (channel portion) of a depletion type reset transistor.
In the above-described CMOS-type solid-state image pickup device, it is assumed that the power source voltage is 3 V, and the gate voltage of the reset transistor 2 is 3 V which is the same as the power source voltage. In this case, in order to completely reset the signal electric charge of the floating diode (electric charge accumulation region N1) by a reset operation, the potential under the gate of the reset transistor 2 is required to be higher (deeper) than 3 V (=the power source voltage) which is the potential of the floating diode and the reset drain.
In FIG. 5, the potential under the gate is higher (deeper) by a magnitude indicated by arrows than the gate voltage. Therefore, by short circuiting (conduction) between the source having a potential of 3 V and the drain, the electric charge accumulation region N1 of the floating diode 3 can be reset to the potential of the voltage reset drain. However, the reset transistor 2 has a characteristic, particularly threshold voltage, which varies according to fluctuations in manufacturing processes. Therefore, this variation needs to be taken into consideration.
FIGS. 6A to 6C show the potentials of the floating diode (assuming that no electric charge is accumulated in the electric charge accumulation region), the reset gate, and the reset drain of the reset transistor 2 when the threshold voltage of the reset transistor 2 is maximum, standard, and minimum, respectively.
When the threshold voltage of the reset transistor 2 goes to a high level, the potential of the reset gate is lowered (upward in FIG. 6) by a variation of the threshold voltage even if a voltage having the same value is applied to the gate. On the other hand, even if fluctuations in manufacturing processes are large to an extent that the threshold voltage of the reset transistor 2 is caused to be maximum, it is necessary to short circuit (conduction) between the floating diode and the reset drain in terms of potential so as to reset the potential of the floating diode. Therefore, taking into consideration variations in threshold voltage, a standard threshold voltage is designed such that even when the threshold voltage of the reset transistor 2 is maximum as shown in FIG. 6A, the potential level of the reset gate is equal to the potential level of the reset drain.
In the case of the standard threshold voltage, the potential of the reset gate is higher (downward in FIG. 6B) than the potential of the reset drain as shown in FIG. 6B.
On the other hand, as indicated by an arrow in FIG. 6C, when the threshold voltage of the reset transistor 2 is minimum, the amount of electric charges which can be accumulated in the floating diode 3 (the electric charge accumulation region N1) is minimum. As shown in FIG. 6A, the standard threshold voltage is designed such that when the threshold voltage of the reset transistor 2 is maximum, the potential level of the reset gate is equal to the potential level of the reset drain. In this case, for example, assuming that the variation in the threshold voltage of the reset transistor 2 is ±0.2 V, when the threshold voltage is minimum, the amount of electric charges which can be accumulated is reduced by a channel potential (0.4 V) two times the variation (±0.2 V) of the threshold voltage as compared to when the threshold voltage is maximum.
Thus, since the threshold voltage of the reset transistor 2 varies due to fluctuations in manufacturing processes, the amount of electric charges which can be stored in the electric charge accumulation region N1 is reduced by a channel potential two times the variation of the threshold voltage of the reset transistor 2.
To solve the above-described problem, the present inventors have proposed a solid-state image pickup device in Japanese Laid-Open Publication No. 9-130681 (entitled “Sold-state Image Pickup Device”), in which a diode device which is a transistor formed by the same process as that for the reset transistor (i.e., having the same structure as that of the reset transistor) and having diode connection, is provided on the same semiconductor substrate. In this device, the forward voltage of the diode device is used as a voltage applied to the gate of the reset transistor.
In this solid-state image pickup device, when the channel potential of the reset transistor varies according to the fluctuations of the manufacturing processes, the channel potential of the transistor contained in the above-described diode device also varies as does the reset transistor. Therefore, the forward voltage of the diode device also varies. The variation in the forward voltage of the diode device causes the voltage applied to the gate of the reset transistor to vary in a manner that cancels the variations in the channel potential. Therefore, even if a characteristic of the reset transistor varies, a desired reset operation can be constantly carried out, thereby making it possible to maintain the maximum amount of accumulated electric charges.
Further, the present inventors have proposed another solid-state image pickup device in Japanese Laid-Open Publication No. 2000-26589 (entitled “Sold-state Image Pickup Device”), in which the solid-state image pickup device further comprises a voltage generation circuit for maintaining the source potential of the reset transistor higher than the channel potential under the gate.
In the solid-state image pickup devices in the above-described publications, the gate of the reset transistor is connected to the gate of the transistor formed by the same process and having the same structure, and the connection point is externally supplied with a reset pulse through a capacitor. Thus, these solid-state image pickup devices require an external capacitor for the gate of the reset transistor. However, such an external capacitor has to be incorporated to the semiconductor substrate in order to reduce the size, weight, and cost of such a solid-state image pickup device.
This external capacitor needs to have a capacitance of about 50 pF in order to hold electric charges for one frame period (e.g., 30 ms). A considerable substrate area is required for providing such an about 50 pF capacitor on a semiconductor substrate, which is not practical. Considering the area occupied by this capacitor on the substrate, the capacitance is preferably within 10 pF. However, a capacitance having a capacitance of 10 pF or less cannot hold electric charges for one frame period (e.g., 30 ms).